About me
I recevied my PhD from Polytechnique Montréal (Canada) under the supervision of Prof. Gabriela Nicolescu at the Heterogeneous Embedded Systems Lab. My interests focus on multicore processing in critical embedded systems. Such architectures bring an increase of computational power at the cost of hazardous execution behaviours called interferences. This research leans toward the mitigation of such interferences. My work is currently applied to the aerospace industry (ARINC-653 compliant RTOS).
Aside from work, I enjoy bike rides, taking pictures, star gazing (astronomy in general), music (composing) and cinema. You can find some of my pictures on my Flickr page.
Contact and Resume
You can access my LinkedIn profile at LinkedIn: Alexy Torres and download my resume by cliking here or contact me using the following email address: alexy(.)torresa(at)gmail(.)com
Publications
The list of my publications is also available on my google Scholar Profile.
Efficient Scheduling, Mapping and Memory Bandwidth Allocation for Safety-Critical Systems
2022
in 20th IEEE International NEWCAS conference
Certifiable Memory Management System for Safety Critical Partitioned System
2022
in ERTS 2022 - 11th European Congress Embedded Real Time Software and Systems
QEMTrace: A Multi-Platform Memory Tracer Based on System Emulation
2020
in Summer Simulation Conference 2020
Simulator-based Framework towards improved cache predictability for multi-core avionic system
2020
in Spring Simulation Conference 2020
Cache locking content selection algorithms for ARINC-653 compliant RTOS
2019
in ACM Transaction on Embedded Computing Systems
Cache Predictability and Performance Improvement in ARINC-653 Compliant Systems
2019
Master Thesis | Polytechnique Montréal
Posters
Efficient Scheduling, Mapping and Memory Bandwidth Allocation for Safety-Critical Systems
2022
in 20th IEEE International NEWCAS conference
Multi-core Safety-Critical Memory Manager
2022
in 57th Design Automation Conference (DAC) Young Fellow
Cache locking content selection algorithms for ARINC-653 compliant RTOS
2019
in ACM Transaction on Embedded Computing Systems
Teaching
Software Tests and Validation Methods
Importance of validation and verification in the software engineering process. Testing and validation methods. Classification of methods. Reminder of structural testing methods and functional testing methods. Test generation for finite automata. Integration and installation test strategies for procedural and object-oriented programming. Statistical approaches to validation and verification. Development methods to ensure reliability. Planning software testing activities.
2021
Teacher Assistant | Undergraduate students level
Oriented Object Programming
Oriented object programming concepts (class, inheritance, polymorphisme). Operation and function overload, exception handling. Dynamic allocation, meta-programmation, basic algorithms (search, sort). Standard library, data structures. GUI and even driven programming.
2020
Lecturer | Undergraduate students level
Embeded System Design and Analysis
This master course introduces the student to typical real time system architectures. The modelisation and temporal specification of the system are explained in details. The class also introduces specification languages for RT system design. Analysis tools are also presented and used during the practicals and RT operating systems are also presented in this course.
2018 - 2023
Teacher Assistant | Graduate students level
Digital Systems Design
Introductory course to FPGA programming with VHDL, a hardware description language. The class presents the basic notions of combinatory and sequential circuits.
2018 - 2023
Teacher Assistant | Undergraduate students level
Projects
Utility Kernel for i386, x86_64 and ARMv7 architectures
UTK is a kernel created for training and educational purposes. It is designed to execute in kernel mode only. It was ported on i386, x86_64 and ARMv7 architectures.
Languages: C, Assembly
QEMTrace
A QEMU based tracer for full system memory accesses. QEMTrace allows bare-metal and OS memory access tracing in a non-intrusive manner.
Language: C
DECA Compiler
DECA is a subset of the Java programming language. In team of 5, we designed and developped a DECA compiler. A light version of the VIM text editor was also developed as a demonstrator of the compiler.
Language: Java
VHDL implementation of a RISC-V architecture
Simplist and non optimized implementation of a RISC-V processor. The RISC-V pipeline is based on the five stage DLX architecture. Implementation: RISC-V32I
Language: VHDL
SAT Solver
SAT Solver by Tristan Stérin and Alexy Torres at the ENS Lyon 2015-2016 TSAT. DPLL based solver with clause choice heuristics and Tseitin tranform.
Language: C++